If you design embedded systems, you know the quiet frustration of BOM bloat. You want a decent core, but suddenly you are routing external High-Speed USB PHYs, hunting down Ethernet transceivers, and fighting PCB trace lengths.
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WCH just took direct aim at that problem. They have officially released the CH32V407 and CH32V467—two 200MHz RISC-V microcontrollers that integrate a 10/100M Ethernet MAC+PHY, dual 480 Mbps USB 2.0 High-Speed PHYs, and up to 8MB of on-chip PSRAM onto a single die.
Here is a breakdown of what this silicon actually packs and where the trade-offs lie.
The Core: 200MHz with Vector Extensions
Both MCUs run on WCH’s in-house Qingke V3V core clocked at 200MHz. Notably, it includes hardware support for the RISC-V Vector (RVV) instruction set extension.
On raw compute, WCH claims a benchmark of 4.11 CoreMark/MHz, which pulls ahead of a standard Arm Cortex-M4.
The memory split defines the two tiers:
- CH32V407: Comes with 200KB SRAM and 512KB Flash, but zero on-chip PSRAM.
- CH32V467: Keeps the 200KB SRAM and 512KB Flash, but stacks on either 4MB or 8MB of on-chip PSRAM.
That extra PSRAM makes the CH32V467 a purpose-built candidate for low-cost HMIs, smart dashboards, and local vision processing where framebuffers usually choke basic internal SRAM.
Peripherals: Heavy on Video, Display, and Connectivity
WCH leaned heavily into multimedia and interface density with this lineup:
- Display & Vision: A dedicated LCD-TFT Controller (LTDC) supporting RGB interfaces with a 24-channel general-purpose DMA engine, paired with a 150MHz Digital Video Port (DVP) to pipe data straight from CMOS camera sensors.
- High-Speed Comms: Two independent USB 2.0 interfaces—both featuring integrated 480 Mbps High-Speed PHYs supporting Host and Device modes—plus integrated Fast Ethernet (10/100Mbps MAC + PHY).
- Storage Expansion: An SDIO interface (supporting MMC, SD/SDIO, and CE-ATA) and an optional FSMC (Flexible Static Memory Controller) for driving external NOR Flash, SRAM, or memory-mapped peripherals.
- Mixed-Signal & Digital I/O: Dual 12-bit DACs, two 12-bit ADCs (16 channels each), on-chip operational amplifiers, and comparators. Digital buses include 1x I2C, 1x I3C, 3x SPI, 10x USART, CAN 2.0B, and 2x I2S audio channels. Up to 77 GPIOs can be mapped across 16 external interrupts.
- Power & Security: Runs at 2.9V–3.6V with Sleep, Stop, and Standby power modes, power-on/power-down reset (POR/PDR), and a programmable voltage detector. Hardware security covers a CRC engine, TRNG, and a 96-bit unique chip ID.
SKU Matrix, Packages, and Pricing
There are six SKUs across three packages (LQFP64, QFN68, and LQFP100):
- CH32V407 Series (No PSRAM): `CH32V407VET6`, `CH32V407WEU6`, `CH32V407RET6`
- CH32V467 Series (4MB/8MB PSRAM): `CH32V467VET6`, `CH32V467WEU6`, `CH32V467RET6`
Variations between SKUs come down to PSRAM capacity, pin count (48 to 77 GPIOs), whether you get one or two High-Speed USB ports, and FSMC availability.
Unit economics are aggressive:
- On AliExpress, 5-packs of the CH32V467RET6 run for $12.15 (~$2.43/chip).
- 5-packs of the CH32V467VET6 run for $14.68 (~$2.94/chip).
- For quick prototyping, AnalogLamb sells breakout development boards for $17.99 (CH32V407) and $21.99 (CH32V467). WCH also has an official CH32V407VET6 evaluation board featuring an RJ45 jack, dual USB ports, and unpopulated LCD pinouts.
Software & Toolchain Status
WCH has posted the full 547-page reference manual, datasheets, EVT firmware packs, and C example code on their portal. For now, the documentation is predominantly in Chinese, with official English translations planned.
On the tooling side, you will be using WCH’s Eclipse-based MounRiver IDE. If you prefer bare-metal hacking via the community-favorite ch32fun SDK, support is not there yet—the CH32V407 codebase has not landed in the upstream repo.
Founder's Take
Getting a 200MHz RISC-V core with vector instructions, 8MB PSRAM, an LCD driver, and built-in HS USB + Fast Ethernet PHYs for under $3 in small quantities shows where edge hardware pricing is heading.
If your product BOM is squeezed by standalone interface transceivers and external RAM chips for a smart display or edge node, this is a platform worth spinning up on the bench.
